This invention relates generally to computer systems, and more particularly to cache memory modules used in computer systems.
In today""s computer systems, the speed of microprocessors has outstripped the speed of typical main memory DRAM systems. When a processor accesses main memory, the processor remains idle for a number of clock cycles, thus wasting precious time. In order to provide as many zero wait state memory accesses as possible, while maintaining a reasonable system cost, many of today""s computer systems provide a high speed SRAM cache module. The faster and more expensive SRAM contains a subset of the slower and less expensive DRAM contents. The memory cache contains copies of data lines from main memory, each line including multiple bytes of data or program instructions (collectively referred to as xe2x80x9cdataxe2x80x9d).
When the microprocessor initiates a memory cycle (read or write), the cache module determines whether it contains a copy of a data line having data at the memory location specified by the microprocessor. If a copy resides in the cache (a cache hit), the microprocessor can achieve a zero wait state memory access. If a copy does not reside in the cache (a cache miss), a main memory access occurs, and the microprocessor remains idle for a number of clock cycles. As the processor operates, the cache contents are regularly changed to include copies of memory lines recently requested by the microprocessor (temporal locality) and to include memory lines in memory locations consecutive to those recently requested (spatial locality).
In the case of a write operation to a memory location having data copied in the cache (a cache write hit), the cache memory is updated, and main memory is then said to contain stale information. The cache line is said to be modified, or dirty, because it is no longer a duplicate of the corresponding line in memory. If main memory is not updated and another bus master (such as a DMA or SCSI controller) accesses main memory, data consistency/coherency problems may result.
Variations on two distinct write policies are employed to prevent data coherency problems. One is called a write-through policy, in which the cache immediately passes each write operation initiated by the microprocessor through to main memory. Even in the case of a cache write hit, both the cache line and the corresponding line in main memory are updated, thereby ensuring consistency between the cache and main memory. The write-through policy is simple to implement, but has the performance limitations associated with each write operation requiring access to the slow main memory.
A second write policy is called a write-back policy, in which main memory is updated only when necessary. This keeps the system bus free for use by other bus masters and is particularly advantageous when significant system I/O activity is expected. Main memory is updated when (1) a bus master other than the microprocessor initiates a read access to a memory line which contains stale data; (2) a bus master other than the microprocessor initiates a write access to a memory line which contains stale data; and (3) a modified cache line is about to be overwritten to store a copy of a memory line newly requested by the microprocessor. When a bus master other than the microprocessor initiates a memory cycle, the cache module must monitor, or snoop, the system bus to check for memory accesses to lines marked as modified in the cache.
Many of today""s microprocessors include an SRAM cache internal to the microprocessor chip. Such a cache is called an L1 cache. Computer system designers may still provide a supplementary external cache, called an L2 cache, to further increase system performance. Maintaining coherency amongst the various caches and main memory is correspondingly more complex than for the exemplary single cache system discussed above, particularly when one or more of the caches employs a write-back policy.
It is oftentimes desirable to allow an end user or manufacturer to decide whether to include the external L2 cache as an upgrade to the computer system. In such a case, the system designer provides a connector for an optional cache module. This reduces manufacturing costs, since a single system board can be used for computer systems with or without an external L2 cache. However, the various control signals necessary to maintain cache coherency must then be routed differently, depending on whether the optional L2 cache module is included. Currently, the alternative routing of the control signals is accomplished with jumpers, which must be physically connected according to whether the L2 cache module upgrade is included. The use of jumpers can be quite inconvenient, particularly for an end user of modest technical sophistication.
According to the present invention, a user-friendly upgradeable cache circuit is provided which automatically routes those control signals necessary to maintain cache coherency. The cache circuit includes a cache module connector and a high speed multiplexer having minimal propagation delay. The multiplexer selects one of two sets of control signals corresponding to the presence or absence of a cache module in the cache module connector.
A computer circuit is provided which includes a controller coupling a processor with main memory. The main memory stores data, and the processor includes an internal cache which stores a subset of the data stored in main memory. The cache circuit is coupled with the processor and with the controller, and includes cache connecting circuitry and switching circuitry. The cache connecting circuitry can receive an optional external cache module and produces a detect signal having a state which indicates whether the external cache module is employed. The switching circuitry responds to the detect signal and inputs to the processor one of two cache inquire signals, depending on the state of the detect signal. One of the cache inquire signals is produced by the controller, and the other is produced by the cache connecting circuitry. The switching circuitry also responds to the detect signal to input to the controller one of two cache content signals, depending on the state of the detect signal. One of the cache content signals is produced by the processor, and the other is produced by the cache connecting circuitry.
A method is provided for controlling cache coherency inquire and write-back cycles in a computer circuit having a controller coupling a processor with a main memory. The processor includes an internal cache, and a cache circuit capable of receiving an optional external cache module is coupled with the controller and the processor. A detect signal is produced. The detect signal has a state which indicates whether the optional external cache module has been employed. First and second cache inquire signals are produced which, when asserted and input to the processor, initiate a cache coherency inquire cycle. Depending on the state of the detect signal, a corresponding one of the first and second cache inquire signals is input to the processor. Also, first and second cache content signals are produced which, when asserted and input to the controller, initiate a cache write back cycle. Depending on the state of the detect signal, a corresponding one of the first and second cache content signals is input to the controller.